enable package:clash-prelude

A signal of booleans, indicating whether a component is enabled. No special meaning is implied, it's up to the component itself to decide how to respond to its enable line. It is used throughout Clash as a global enable signal.

Enable generator for some domain. Is simply always True.

Determine whether a write enable is active

Merge global enable with write enable

Merge enable signal with signal of bools by applying the boolean AND operation.

Convert Enable construct to its underlying representation: a signal of bools.

Convert a signal of bools to an Enable construct

Enable signal that's always enabled. Because it has a blackbox definition this enable signal is opaque to other blackboxes. It will therefore never be optimized away.

A constraint that indicates the component needs a Clock, a Reset, and an Enable belonging to the same dom. Click here to read more about hidden clocks, resets, and enables

A constraint that indicates the component needs an Enable Click here to read more about hidden clocks, resets, and enables

A constraint that indicates the component needs a Clock, a Reset, and an Enable belonging to the System domain. Click here to read more about hidden clocks, resets, and enables

Merge enable signal with signal of bools by applying the boolean AND operation. NB: The component given to andEnable as an argument needs an explicit type signature. Please read Monomorphism restriction leads to surprising behavior. The component whose enable is modified will only be enabled when both the encompassing HiddenEnable and the Signal dom Bool are asserted. Click here to read more about hidden clocks, resets, and enables

Example

Usage with a polymorphic domain:

>>> reg = register 5 (reg + 1)

>>> f en = andEnable en reg

>>> sampleN @System 10 (f (riseEvery d2))
[5,5,5,6,6,7,7,8,8,9]

Force andEnable to work on System (hence sampleN not needing an explicit domain later):

>>> reg = register 5 (reg + 1)

>>> f en = andEnable @System en reg

>>> sampleN 10 (f (riseEvery d2))
[5,5,5,6,6,7,7,8,8,9]

Expose hidden Clock, Reset, and Enable arguments of a component, so they can be applied explicitly. Click here to read more about hidden clocks, resets, and enables

Example

Usage with a polymorphic domain:

>>> reg = register 5 (reg + 1)

>>> sig = exposeClockResetEnable reg clockGen resetGen enableGen

>>> sampleN @System 10 sig
[5,5,6,7,8,9,10,11,12,13]

Force exposeClockResetEnable to work on System (hence sampleN not needing an explicit domain later):

>>> reg = register 5 (reg + 1)

>>> sig = exposeClockResetEnable @System reg clockGen resetGen enableGen

>>> sampleN 10 sig
[5,5,6,7,8,9,10,11,12,13]

Usage in a testbench context:

topEntity :: Vec 2 (Vec 3 (Unsigned 8)) -> Vec 6 (Unsigned 8)
topEntity = concat

testBench :: Signal System Bool
testBench = done
where
testInput      = pure ((1 :> 2 :> 3 :> Nil) :> (4 :> 5 :> 6 :> Nil) :> Nil)
expectedOutput = outputVerifier' ((1:>2:>3:>4:>5:>6:>Nil):>Nil)
done           = exposeClockResetEnable (expectedOutput (topEntity <$> testInput)) clk rst en
clk            = tbSystemClockGen (not <$> done)
rst            = systemResetGen
en             = enableGen

Expose a hidden Enable argument of a component, so it can be applied explicitly. Click here to read more about hidden clocks, resets, and enables

Example

Usage with a polymorphic domain:

>>> reg = register 5 (reg + 1)

>>> sig = exposeEnable reg enableGen

>>> sampleN @System 10 sig
[5,5,6,7,8,9,10,11,12,13]

Force exposeEnable to work on System (hence sampleN not needing an explicit domain later):

>>> reg = register 5 (reg + 1)

>>> sig = exposeEnable @System reg enableGen

>>> sampleN 10 sig
[5,5,6,7,8,9,10,11,12,13]

Connect a hidden Enable to an argument where a normal Enable argument was expected. Click here to read more about hidden clocks, resets, and enables

Hide the Clock, Reset, and Enable arguments of a component, so they can be routed implicitly. Click here to read more about hidden clocks, resets, and enables

Hide the Enable argument of a component, so it can be routed implicitly. Click here to read more about hidden clocks, resets, and enables

Connect an explicit Clock, Reset, and Enable to a function with a hidden Clock, Reset, and Enable. Click here to read more about hidden clocks, resets, and enables

Example

Usage with a polymorphic domain:

>>> reg = register 5 (reg + 1)

>>> sig = withClockResetEnable clockGen resetGen enableGen reg

>>> sampleN @System 10 sig
[5,5,6,7,8,9,10,11,12,13]

Force withClockResetEnable to work on System (hence sampleN not needing an explicit domain later):

>>> reg = register 5 (reg + 1)

>>> sig = withClockResetEnable @System clockGen resetGen enableGen reg

>>> sampleN 10 sig
[5,5,6,7,8,9,10,11,12,13]

Connect an explicit Enable to a function with a hidden Enable. Click here to read more about hidden clocks, resets, and enables

Example

Usage with a polymorphic domain:

>>> reg = register 5 (reg + 1)

>>> sig = withEnable enableGen reg

>>> sampleN @System 10 sig
[5,5,6,7,8,9,10,11,12,13]

Force withEnable to work on System (hence sampleN not needing an explicit domain later):

>>> reg = register 5 (reg + 1)

>>> sig = withEnable @System enableGen reg

>>> sampleN 10 sig
[5,5,6,7,8,9,10,11,12,13]