cycle package:clash-prelude

cycle :: [a] -> [a]
clash-prelude Clash.HaskellPrelude
cycle ties a finite list into a circular one, or equivalently, the infinite repetition of the original list. It is the identity on infinite lists.
cycleBoth :: forall nAddrs a writeEnable . (NFDataX a, HasCallStack) => SNat nAddrs -> TdpbramModelConfig writeEnable a -> a -> a -> Seq a -> (MaybeX Bool, MaybeX Int, MaybeX writeEnable, a) -> (MaybeX Bool, MaybeX Int, MaybeX writeEnable, a) -> (Seq a, a, a)
clash-prelude Clash.Explicit.BlockRam.Model
Step through a cycle of a TDP block RAM where the clock edges of port A and port B coincided. Like accessRam, it accounts for XException in all values supplied by the user of the block RAM.
cycleOne :: forall nAddrs a writeEnable . (HasCallStack, NFDataX a) => SNat nAddrs -> TdpbramModelConfig writeEnable a -> a -> Seq a -> (MaybeX Bool, MaybeX Int, MaybeX writeEnable, a) -> (Seq a, a)
clash-prelude Clash.Explicit.BlockRam.Model
Step through a cycle of a TDP block RAM where only one clock is active. Like accessRam, it accounts for XException in all values supplied by the user of the block RAM.