seq package:clash-prelude
The value of seq a b is bottom if a is bottom, and
otherwise equal to b. In other words, it evaluates the first
argument a to weak head normal form (WHNF). seq is
usually introduced to improve performance by avoiding unneeded
laziness.
A note on evaluation order: the expression seq a b does
not guarantee that a will be evaluated before
b. The only guarantee given by seq is that the both
a and b will be evaluated before seq
returns a value. In particular, this means that b may be
evaluated before a. If you need to guarantee a specific order
of evaluation, you must use the function pseq from the
"parallel" package.
Evaluate all elements of a vector to WHNF, returning the second
argument
Evaluate all elements of a vector to WHNF, returning the second
argument. Does not propagate
XExceptions.
Evaluate each monadic action in the structure from left to right, and
collect the results. For a version that ignores the results see
sequence_.
Evaluate each action in the structure from left to right, and collect
the results. For a version that ignores the results see
sequenceA_.
Evaluate each monadic action in the structure from left to right, and
ignore the results. For a version that doesn't ignore the results see
sequence.
As of base 4.8.0.0,
sequence_ is just
sequenceA_,
specialized to
Monad.
Sequential composition of two
DataFlow circuits.
Like
seqX, but will also catch ErrorCall exceptions which are
thrown. This should be used with care.
seqErrorX (ErrorCall msg) b = b
seqErrorX (XException msg) b = b
seqErrorX _|_ b = _|_
Like
seq, however, whereas
seq will always do:
seq _|_ b = _|_
seqX will do:
seqX (XException msg) b = b
seqX _|_ b = _|_
deepseqX: fully evaluates the first argument, before returning
the second. Does not propagate
XExceptions.
Like
seqX in simulation, but will force its first argument to
be rendered in HDL. This is useful for components that need to be
rendered in hardware, but otherwise have no meaning in simulation. An
example of such a component would be an ILA: a component monitoring an
internal signal of a design. The output of such a component (typically
a unit) can be passed as the first argument to
hwSeqX to ensure
the ILA ends up in the generated HDL.
NB: The result of
hwSeqX must (indirectly) be used at
the very top of a design. If it's not, Clash will remove it like it
does for any other unused circuit parts.
NB: Make sure the blackbox for the component with zero-width
results uses
RenderVoid